As the downsizing and high operability of semiconductor devices have been required, for forming interconnection layers of the recent semiconductor devices, the so-called damascene method, in which trench patterns and hole patterns are formed in an inter-layer insulating film, and an interconnection material is buried in the trenches and holes, is used. As the interconnection material, copper (Cu), which is less resistive than aluminum, is used in place of aluminum conventionally used.
Copper is a metal material which tends to diffuse into silicon oxide film which is the main material of the inter-layer insulating film. There is a risk that copper diffusing in the inter-layer insulating film will cause short circuits and defects of the interconnections. When copper is used as the interconnection material, it is preferable that a barrier layer for preventing the diffusion of the copper is provided on the inside walls of the trenches and holes to thereby prevent the diffusion of the copper into the inter-layer insulating film. Conventionally, as the barrier layer materials, barrier metal materials, such as titanium (Ti), tantalum (Ta), etc., have been used.
The following is a example of related: Japanese Laid-open Patent Publication No. 09-252095.
However, titanium and tantalum, which are the conventionally used barrier layer materials, have low oxidation resistance and are often oxidized by the heat generated by the thermal processing of backend process or the heating during the operation. The oxidation of the barrier layer causes a risk that the interconnection resistance would rise and increase the interconnection delay, and the yield and reliability would decrease. Processing techniques for suppressing the oxidation of the barrier layer, and barrier layer materials of high oxidation resistance are required. It is also important that the barrier layer for the copper interconnections can be formed at a low temperature which is applicable to the backend process.